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GALVANTECH, INC. ASYNCHRONOUS SRAM
FEATURES
* * * * * * * * * Fast access times: 10, 12, 15and 20ns Fast OE# access times: 5, 6, 7 and 8ns Single +5V +10% power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE# and OE# options Automatic CE# power down High-performance, low-power consumption, CMOS double-poly, double-metal process
GVT72028A4 TRADITIONAL PINOUT 256K X 4
256K x 4 SRAM
WITH SINGLE CHIP ENABLE TRADITIONAL PINOUT
GENERAL DESCRIPTION
The GVT72028A4 is organized as a 262,144 x 4 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#) and output enable (OE#) with this organization. Writing to these devices is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW. Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
OPTIONS
* Timing 10ns access 12ns access 15ns access 20ns access Packages 28-pin SOJ (400 mil) 28-pin SOJ (300 mil) Power consumption Standard Low Temperature Commercial Industrial
MARKING
-10 -12 -15 -20
*
J SJ
PIN ASSIGNMENT 28-Pin SOJ
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE# OE# VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
*
None L
* *
None I
(0C to 70C) (-40C to 85C)
*
Part Number Examples
PART NO. Pkg
GVT72028A4J-10L
28-pin SOJ (400 mil)
VCC A6 A5 A4 A3 A2 A1 A0 NC DQ4 DQ3 DQ2 DQ1 WE#
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699
Rev. 1/97
Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
GVT72028A4 TRADITIONAL PINOUT 256K X 4
VCC VSS A0 DQ1
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY 512 ROWS X 512 X 4 COLUMNS
I/O CONTROL
DQ4
CE# WE#
OE#
A17
COLUMN DECODER
POWER DOWN
TRUTH TABLE
MODE READ WRITE OUTPUT DISABLE STANDBY CE# L L L H WE# H L H X OE# L X H X DQ Q D HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY
PIN DESCRIPTIONS
SOJ Pin Numbers
21-27, 1-11 15 12
SYMBOL
A0-A17 WE# CE#
TYPE
Input
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed. Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into standby power mode.
Input
13 16, 17, 18, 19 28 14
OE# DQ1-DQ4 VCC VSS
Input Output Enable: This active LOW input enables the output drivers. Input/Output SRAM Data I/O: Data inputs and data outputs Supply Supply Power Supply: 5V +10% Ground
January 10, 1997
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
GVT72028A4 TRADITIONAL PINOUT 256K X 4
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA
*Stresses greater than those listed under "Absolute Maximum
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 5V +10% unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA
CONDITIONS
SYMBOL
VIH VIl ILI ILO VOH VOL VCC
MIN
2.2 -0.5 -5 -5 2.4
MAX
VCC+1 0.8 5 5
UNITS
V V uA uA V
NOTES
1, 2 1, 2
1 1 1
0.4 4.5 5.5
V V
DESCRIPTION
Power Supply Current: Operating TTL Standby CMOS Standby
CONDITIONS
Device selected; CE# < VIL; VCC =MAX; f=fMAX; outputs open CE# >VIH; VCC = MAX; f=fMAX CE# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0
SYM
Icc ISB1 ISB2
TYP
80 20 0.75
POWER
-10
240 210 60 45 5 5
-12
220 180 55 40 5 5
-15
180 150 50 35 5 5
-20
140 110 40 30 7 7
UNITS NOTES mA mA mA 3, 14 14 14
standard low standard low standard low
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 5V
SYMBOL
CI CI/O
MAX
6 8
UNITS
pF pF
NOTES
4 4
January 10, 1997
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 5V
DESCRIPTION
READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Enable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z
tWC tCW tAW tAS tAH tWP2 tWP1 tDS tDH tLZWE tHZWE tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tPU tPD
GVT72028A4 TRADITIONAL PINOUT 256K X 4
+10%)
- 10 - 12
MIN MAX
- 15
MIN MAX
- 20
MIN MAN UNITS NOTES
SYM
MIN
MAX
10 10 10 3 3 5 5 0 5 0 10 10 8 8 0 0 10 8 6 0 3 5
12 12 12 4 4 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 4 6
15 15 15 4 4 7 7 0 7 0 15 15 9 9 0 0 11 9 7 0 5 7
20 20 20 4 4 8 8 0 8 0 20 20 10 10 0 0 12 10 8 0 5 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 6 4 4 4, 7 4, 6, 7
January 10, 1997
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT72028A4 TRADITIONAL PINOUT 256K X 4
OUTPUT LOADS
Q Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT +5V 480 Q 255 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. 8. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +7.0V for t tRC /2. VIL -2.0V for t tRC /2
9.
Device is continuously selected. Chip enable and output enables are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 5V, 25oC and 20ns cycle time.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. WE# is HIGH for READ cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
Vcc for Retention Data Data Retention Current CE# >VCC -0.2; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 Vcc = 2V Vcc = 3V
CONDITIONS
SYMBOL
MIN
2
TYP
MAX
UNITS
V
NOTES
VDR ICCDR ICCDR tCDR tR
100 200 0
500 750
uA uA ns ns
13 13 4 4, 11
Chip Deselect to Data Retention Time Operation Recovery Time
tRC
January 10, 1997
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
GVT72028A4 TRADITIONAL PINOUT 256K X 4
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VIH VIL
4.5V
t
VDR
4.5V
tRC
CDR
CE#
READ CYCLE NO. 1(8, 9)
tRC
ADDR
tAA tOH
VALID
Q
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
tRC
DATA VALID
CE#
tAOE tLZOE
OE#
tACE tLZCE
tHZCE
tHZOE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED
January 10, 1997
6
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
GVT72028A4 TRADITIONAL PINOUT 256K X 4
WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW))
t
WC
ADDR
t
AW
t
t
AH
CW
CE#
tAS
tWP2
WE#
tDS tDH
D
tHZWE
DATA VALID
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH)
t WC
ADDR
tAW t t AH
CW
CE#
tAS tWP1
WE#
tDS tDH
D Q
DATA VALID HIGH Z DON'T CARE UNDEFINED
January 10, 1997
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
GVT72028A4 TRADITIONAL PINOUT 256K X 4
WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled)
t
WC
ADDR
tAW t tAH t
AS
CW
CE#
tWP1
WE#
tDS tDH
D
DATA VALID HIGH Z
Q
DON'T CARE
January 10, 1997
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
Package Dimensions
GVT72028A4 TRADITIONAL PINOUT 256K X 4
28-pin 400 Mil Plastic SOJ (J)
.730 (18.54) .720 (18.29)
.405 (10.29) .395 (10.03)
.445 (11.30) .435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP
.145 (3.68) .131 (3.33)
SEATING PLANE .020 (0.51) .015 (0.38)
.095 (2.41) .080 (2.03) .380 (9.65) .360 (9.14) .030 (0.76) MIN
MAX Note: All dimensions in inches (millimeters) MIN
or typical, min where noted.
28-pin 300 Mil Plastic SOJ (SJ)
.730 (18.54) .697 (17.70)
.305 (7.75) .292 (7.42)
.347 (8.81) .327 (8.31)
PIN #1 INDEX
.050 (1.27) TYP
.140 (3.54) .120 (3.04)
SEATING PLANE .020 (0.51) .014 (0.36)
.095 (2.41) .080 (2.03) .275 (6.99) .260 (6.60) .025 (0.63) MIN
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, min where noted.
January 10, 1997
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97
GALVANTECH,
Ordering Information
GVT72028A4 TRADITIONAL PINOUT 256K X 4
GVT 72028A4 XX - XX X X
Galvantech Prefix Part Number Temperature (Blank = Commercial I = Industrial) Power (Blank= Standard, L= Low Power) Speed (10 = 10ns, 12= 12ns 15 = 15ns, 20 = 20ns) Package (J = 400 mil SOJ, SJ= 300 mil SOJ)
January 10, 1997
10
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/97

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